`timescale 1ns/1ps
module StateFlipFlop(iPME, iPM, iPC, iPCE, iRC, iRCE, iRME, iCS, oPME, oPM, oPC, oPCE, oRC, oRCE, oRME, oCS);
input iPME;
input [1:0] iPM;
input [23:0] iPC;
input iPCE;
input [23:0] iRC;
input iRCE;
input iRME;
input [23:0] iCS;

output oPME;
output [1:0] oPM;
output [23:0] oPC;
output oPCE;
output [23:0] oRC;
output oRCE;
output oRME;
output [23:0] oCS;

wire iPME;
wire [1:0] iPM;
wire [23:0] iPC;
wire iPCE;
wire [23:0] iRC;
wire iRCE;
wire iRME;
wire [23:0] iCS;
reg oPME;
reg [1:0] oPM;
reg [23:0] oPC;
reg oPCE;
reg [23:0] oRC;
reg oRCE;
reg oRME;
reg [23:0] oCS;

task attend;
  begin
  if(iPME == 1'b1) begin
      oPME <= iPME;
      oPM <= iPM;
      oPCE = 1'b0;
      oRCE = 1'b0;
      oRC = 24'bx;
      oRME = 1'b0;
      oCS = 24'bx;
    end
  else if(iPCE == 1'b1) begin
      oPCE = 1'b1;
      oPC <= iPC;
      oPME = 1'b0;
      oPM = 2'b0;
      oRME = 1'b0;
      oRCE = 1'b0;
      oRC = 24'b0;
      oCS = 24'b1;
    end
  else if(iRCE == 1'b1) begin
      oRCE = 1'b1;
      oRC <= iRC;
      oPCE = 1'b0;
      oPC = 24'b0;
      oPME = 1'b0;
      oPM = 2'b0;
      oRME = 1'b0;
      oCS = 24'b1;
    end
  else if(iRME == 1'b1) begin
      oRME = 1'b1;
      oPME = 1'b0;
      oPM = 2'b0;
      oPC = 24'b1;
      oPCE = 1'b0;
      oRC = 24'b1;
      oRCE = 1'b0;
      oCS = 24'b1;
    end
  else if(iCS != 24'b1 || iCS != 24'bx) begin
      oCS <= iCS;
      oPME = 1'b0;
      oPM = 2'b0;
      oPC = 24'b1;
      oPCE = 1'b0;
      oRC = 24'b1;
      oRCE = 1'b0;
      oRME = 1'b0;
    end
  else
    begin
    //do nothing, Idle state
    end
  end
endtask;

endmodule

